SEU Tolerance Efficiency of Multiple Layout-Hardened 28 nm DICE D Flip-Flops
نویسندگان
چکیده
Three layout-hardened Dual Interlocked Storage Cell (DICE) D Flip-Flops (DFFs) were designed and manufactured based on an advanced 28 nm planar technology. The systematic vertical tilt heavy ion irradiations demonstrated that the DICE structure contributes to radiation tolerance. However, it is hard achieve immunity from a Single Event Upset (SEU), even when ~3-µm well isolation utilized. SEU mitigation of hardened DFFs was affected by data patterns clock signals due imbalance in number upset nodes. When signal equalled 0, no error observed 181Ta irradiation, indicating are tolerant irradiation owing their reasonable sensitive volumes. divergences cross-sections enlarged our specially joint change incidences for both along-cell cross-cell ions. evaluations assist with eliminating overestimation tolerance guarantee in-orbit safety spacecraft harsh environments.
منابع مشابه
SEU-Resistant Magnetic Flip Flops
The development of a practical magnetic tunneling junction (MTJ) ten years ago allowed the creation of a new class of non-volatile memories. This technology may offer superior resistance to total ionizing dose and virtually unlimited write endurance, making it more attractive than flash memories for space applications. Although a number of manufacturers are developing high-density bulk magnetic...
متن کاملEnhancing Robust SEU Mitigation with 28-nm FPGAs
Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability, high-reliability, and safety-critical systems. However, along with technology scaling come other effects such as increased susceptibility to soft errors that previously could be ignored. These soft error...
متن کاملA 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flops
We propose a low-power redundant flip-flop to be operated with high reliability over 1GHz clock frequency based on the low-power ACFF and the highly-reliable BCDMR FF. Its power dissipation is almost equivalent to transmission gate FFs at 10% data activity while paying 3x area penalty. Experiments by α-particle and neutron irradiation reveals its highly-reliable operations with no errors at 1.2...
متن کاملAn Innovative Radiation Hardened By Design Flip - Flop
i ABSTRACT Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets...
متن کاملLow Power Dissipation SEU-hardened CMOS Latch
This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is show...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Electronics
سال: 2022
ISSN: ['2079-9292']
DOI: https://doi.org/10.3390/electronics11070972